The invention relates to a method for improving buried channel integrated circuit devices, and more specifically, to a method for producing reduced size semiconductor devices having reduced electric fields and high breakdown voltages.
To continuously improve performance, the size of semiconductor devices has been steadily scaled down. The physics of the scaling laws are complex. But for MOSFETs (Metal Oxide Silicon Field Effect Transistors), a major limiting factor is the presence of high electric fields. The electric field maximum tends to occur around the body/drain junction near the silicon/silicon dioxide interface, just below the edge of the gate. This high electric field can cause reliability and/or operational problems. Reliability problems result when the electric field generates very energetic or `hot` carriers. The hot carriers are injected into the gate oxide, degrading the gate oxide quality. Operational problems result when the electric field is high enough to result in avalanche ionization. In avalanche ionization, a few carriers receive enough energy to generate other carriers, which in turn receive enough energy to generate even more carriers, and so on.
The avalanche ionization effect is a particular problem in SOI (silicon-on-insulator) devices. The reason for this is that in SOI devices, the active area is separated from the bulk of the wafer by an electrical insulator (e.g. silicon oxide, silicon nitride, or sapphire). Thus, the body of the device is at a floating electric potential. Since the body is floating, minority carriers (holes in n-channel devices, electrons in p-channel devices) collect in the body, near the source/body junction. For example, in n-channel devices, when the hole concentration changes the body potential, electrons are injected from the source. Many of these electrons reach the drain, where they participate in impact ionization. The resulting positive feedback loop results in a runaway current at electric fields levels significantly below the junction breakdown voltage.
A number of approaches for improving the maximum operating voltage in a semiconductor device have been proposed. None of the proposed means for reducing the maximum operating voltage does so without increasing the resistance in the transistor. Most techniques require special tooling or difficult processing steps and are not readily applicable to SOI technology.